In the design of integrated circuits, the voltages representative of logic signals at the core of the integrated circuit are often lower than the voltage levels associated with logic signals used by input/output (I/O) sections of the integrated circuit or devices external to the integrated circuit. Accordingly, level shifting circuits or voltage translating circuits are used to shift or translate voltage signals representative of logic levels or data at the core of the integrated circuit to higher voltage levels representative of the same data for use with I/O circuit sections or output devices.
For instance, microprocessors, programmable logic devices, memory devices, timing and clock devices or circuits, all contain I/O interfaces which operate at different voltage levels than the core of the respective integrated circuit. In one example, a core logic voltage level may be zero to 1.8 volts, wherein zero volts is representative of “low” signal, and 1.8 volts is representative of a “high” logic signal. Alternatively, a “high” logic signal may be represented as, for instance, 2.5 volts at the core. These logic levels at the core of the integrated circuit are translated using level shifting circuits or voltage translators to higher voltage levels, such as, in one example, zero to 3.3 volts, wherein zero volts represents a logic “low” level, and 3.3 volts represents a logic “high” level.
FIG. 1 illustrates an example of a voltage translating circuit 10 which can be used with an integrated circuit having a core. An integrated circuit including the circuit of FIG. 1 uses two different types of transistors (known as dual gate IC process technology), one transistor type with a high voltage oxide gate breakdown (i.e., high voltage transistors) for the level shifting circuit 10, and another transistor type with a low voltage oxide gate breakdown (i.e., low voltage transistors) used in the core.
Referring to FIG. 1, circuit 10 uses high voltage transistors including a p-channel transistor 12 in parallel with a p-channel transistor 14 having its gate coupled with the drains of the parallel connection of p-channel transistors 16 and 18, wherein the gate of transistor 16 is coupled with the drains of transistors 12 and 14. N-channel transistors 20 and 22 have their drains connected to the drains of parallel transistors 12 and 14 and parallel transistors 16 and 18, respectively. The gate of transistor 20 receives input data from the core of the integrated circuit, while the gate of transistor 22 receives through inverter 24 the complement of the input data signal from the core. In this circuit, an output signal may be taken from the drain of transistor 22, while the complement of the output signal may be taken from the drain of transistor 20.
In operation, when the input data signal 25 is low, transistor 20 turns off which allows the drain of transistor 20 to float. Because the input data signal 25 is low, inverter 24 provides a high signal to the gate of transistor 22, and transistor 22 is on and the output signal 26 goes low, which turns transistor 14 on, which charges up the output complement signal 28 to a high level. The high level on the complement output signal 28 also turns transistor 16 off which allows transistor 22 to pull or hold output signal 26 at a low logic level.
When the input data signal 25 from the core is at a high logic level, this turns transistor 22 off and allows the output signal 26 to float. Transistor 20 is on, and accordingly, the output signal 28 is at a low logic level, which turns transistor 16 on which charges up the output signal 26 to a high logic level, which turns transistor 14 off, thereby allowing transistor 20 to pull down the output signal 28 to a logic low level.
In the example of FIG. 1, the core of the integrated circuit may use low voltage oxide gate breakdown transistors, and the circuit 10 may utilize high voltage oxide gate breakdown transistors for performing the level shifting operations.
However, as recognized by the present inventor, forming an integrated circuit through the use of dual gate IC processes increases the complexity and cost of the integrated circuit design. Further, the circuit 10 of FIG. 1 draws standby current even when the circuit is not translating or switching, and general reductions in the standby current have a tendency to slow down the operation of the translating circuit, which is undesirable for high performance, low power applications.
Further, as recognized by the present inventor, an integrated circuit formed using dual gate IC designs may not in some instances be easily adaptable or portable to different circuit I/O supply environments or designs, since the output 26 of circuit 10 may be sensitive to the width ratios of transistors 18 and 22 or 12 and 20, in one example. Furthermore, as recognized by the present inventor, in dual gate integrated circuit processes, there may be a tradeoff between the long term reliability of the voltage translating circuit and the speed of the switching of the translating circuit because larger signal swings are desirable for faster translation speeds; however, such larger signals swings may degrade the long term reliability of the device by imposing an unacceptably high level of voltage stress on switching elements of the translating circuit.
As recognized by the present inventors, what is needed is a circuit for shifting the voltage levels of an input signal to higher voltage levels, wherein the circuit is formed using the same process/type of transistors as is used in the core of the integrated circuit.
It is against this background that various embodiments of the present invention were developed.